The present invention relates to a method and a circuit for controlling a DC--DC converter, and more particularly, to a method and a circuit for controlling a DC--DC converter that generates the operational power for portable electronic equipment and the charging power of a battery used in such electronic equipment.
Portable electronic equipment, such as notebook computers, include a DC--DC converter which generates system power and battery charging power from a DC power supply provided by an external AC adapter. The DC--DC converter is set such that the sum of the system consumption current and the battery charging current is smaller than the current supply capacity of the AC adapter. This is because an overcurrent limiter of the AC adapter inhibits the current output when the value of the current sum becomes greater than the AC adapter's current supply capacity. Thus, it is advantageous if the DC--DC converter can make full use of the entire current supply capacity.
FIG. 1 is a schematic diagram showing a first prior art example of a DC--DC converter 100. The DC--DC converter 100 includes a control circuit 2 and a plurality of external elements. The control circuit 2 and the external elements are formed in the same semiconductor integrated circuit. The control circuit 2 outputs a signal SG1 to the gate of an output transistor 3, which is preferably an enhancement type PMOS transistor. An AC adapter 4 provides a DC power supply voltage Vin to the source of the output transistor 3 via a resistor R1. The DC power supply voltage Vin is also provided to an output terminal EX1 via the resistor R1 and a diode D1. The output voltage Vout1 is provided to an electronic device from the output terminal EX1. The drain of the output transistor 3 is connected to a charging output terminal EX2 via an output coil 5 and a resistor R2. The charging output terminal EX2 is connected to the output terminal EX1 via a diode D2. The output voltage Vout2 is provided to a battery BT from the charging output terminal EX2.
The drain of the output transistor 3 is also connected to the cathode of a flywheel diode 6, which may be a Schottky diode. The anode of the flywheel diode 6 is connected to a ground GND. The node between the output coil 5 and the resistor R2 is connected to the ground GND via a smoothing capacitor 7. The smoothing capacitor 7 and the output coil 5 form a smoothing circuit which smoothes the output voltage Vout2.
The control circuit 2 includes a first current detection amplifying circuit 11, a second current detection amplifying circuit 12, first, second, and third error amplifying circuits 13, 14, 15, a PWM comparison circuit 16, a triangular wave oscillating circuit 17, and an output circuit 18.
The first current detection amplifying circuit 11 has an inverting input terminal connected to the low potential terminal of the resistor R1 and a non-inverting input terminal connected to the high potential terminal of the resistor R1. The amplifying circuit 11 detects the value of the current I0 supplied by the AC adapter 4 and provides the first error amplifying circuit 13 with a first voltage signal SG2 corresponding to the current value. An increase in the supply current I0 increases the potential of the first voltage signal SG2. A decrease in the supply current I0 decreases the potential of the first voltage signal SG2. The supply current I0 is equal to the sum of the output current I1 of the output terminal EX1 and the charging current I2 (flowing through the resistor R2) provided to the battery BT by the charging output terminal EX2.
The first error amplifying circuit 13 has an inverting input terminal, which is provided with the first voltage signal SG2, and a non-inverting input terminal, which is provided with a first reference voltage Vref1. The first error amplifying circuit 13 compares the first voltage signal SG2 with the first reference voltage Vref1 and amplifies the voltage difference to generate a first error output signal SG3, which is provided to the PWM comparison circuit 16. An increase in the potential of the first voltage signal SG2 decreases the potential of the first error output signal SG3, and a decrease in the potential of the first voltage signal SG2 increases the potential of the first error output signal SG3.
The second current detection amplifying circuit 12 has an inverting input terminal connected to the low potential terminal of the resistor R2 and a non-inverting input terminal connected to the high potential terminal of the resistor R2. The amplifying circuit 12 detects the value of the charging current I2 supplied to the battery BT and provides the second error amplifying circuit 14 with a second voltage signal SG4 corresponding to the detected value. An increase in the charging current I2 increases the potential of the second voltage signal SG4. A decrease in the charging current I2 decreases the potential of the second voltage signal SG4.
The second error amplifying circuit 14 has an inverting input terminal, which is provided with the second voltage signal SG4, and a non-inverting input terminal, which is provided with a second reference voltage Vref2. The second error amplifying circuit 14 compares the second voltage signal SG4 with the second reference voltage Vref2 and amplifies the voltage difference to generate a second error output signal SG5, which is provided to the PWM comparison circuit 16. An increase in the potential of the second voltage signal SG4 decreases the potential of the second error output signal SG5, and a decrease in the potential of the second voltage signal SG4 increases the potential of the second error output signal SG5.
The third error amplifying circuit 15 has an inverting input terminal, which is provided with the output voltage Vout2, and a non-inverting input terminal, which is provided with a third reference voltage Vref3. The third error amplifying circuit 15 compares the output voltage Vout2 with the third reference voltage Vref3 and amplifies the voltage difference to generate a third error output signal SG6, which is provided to the PWM comparison circuit 16. An increase in the voltage Vout2 decreases the potential of the third error output signal SG6, and a decrease in the output voltage Vout2 increases the potential of the third error output signal SG6.
The PWM comparison circuit 16 has a first non-inverting input terminal which receives the first error output signal SG3, a second non-inverting input terminal which receives the second error output signal SG5, a third non-inverting input terminal which receives the third error output signal SG6, and an inverting input terminal which receives a triangular wave signal SG7 from the triangular wave oscillating circuit 17.
Among the first, second, and third error output signals SG3, SG5, SG6, the PWM comparison circuit 16 selects the signal having the lowest level and compares the selected signal with the triangular wave signal SG7. When the triangular wave signal SG7 is greater than the selected signal, the PWM comparison circuit 16 provides a duty control signal SG8 having a low level to the output circuit 18. When the triangular wave SG7 is smaller than the selected signal, the PWM comparison circuit 16 outputs a duty control signal SG8 having a high level to the output circuit 18. The output circuit 18 inverts the duty control signal SG8, and provides the output signal (inverted duty control signal) SG1 to the gate of the output transistor 3. The output transistor 3 is activated and deactivated in response to the output signal SG1 and thus, maintains the supply current I0, the charging circuit I2, and the output voltage Vout2 at predetermined values.
More specifically, if, for example, the supply current I0 of the AC adapter 4 increases, the potential of the first voltage signal SG2 increases and the potential of the first error output signal SG3 decreases. If the potential of the first error output signal SG3 becomes smaller than the potentials of the second and third error output signals SG5, SG6, the comparison circuit 16 compares the first error output signal SG3 and the triangular wave signal SG7 and generates the duty control signal SG8 such that the duty control signal SG8 remains high over a short period of time (i.e., has a low duty ratio). That is, a decrease in the potential of the first error output signal SG3 prolongs the period during which the potential of the triangular wave signal SG7 exceeds the potential of the error output signal SG3.
A decrease in the duty ratio of the duty control signal SG8 increases the duty ratio of the output signal SG1 and shortens the activated time of the output transistor 3. This decreases the charging current I2 and the supply current I0. The decrease of the supply current I0 decreases the potential of the first voltage signal SG2 and increases the potential of the first error output signal SG3. This causes the duty control signal SG8 to remain high for a long period (i.e., to have a high duty ratio). That is, an increase in the potential of the first error output signal SG3 shortens the period during which the potential of the triangular wave signal SG7 exceeds the potential of the error output signal SG3.
The increase in the duty ratio of the duty control signal SG8 lowers the duty ratio of the output signal SG1 and prolongs the activated period of the output transistor 3. This increases the charging current I2 and the supply current I0. This operation is repeated until the supply current I0 of the AC adapter 4 converges on a predetermined value. That is, until the first voltage signal SG2 converges on a first reference voltage Vref1.
If, for example, the-charging current I2 sent to the battery BT increases, the potential of the second voltage signal SG4 increases and the potential of the second error output signal SG5 decreases. When the potential of the second error output signal SG5 becomes smaller than the potentials of the first and third error output signal SG3, SG6, the comparison circuit 16 compares the second error output signal SG5 with the triangular wave signal SG7 and generates a duty control signal SGB that remains high for a short period (i.e., has a low duty ratio). In other words, a decrease in the potential of the second error output signal SG5 prolongs the period during which the potential of the triangular wave signal SG3 exceeds the potential of the error output signal SG5.
The decrease in the duty ratio of the duty control signal SG8 increases the duty ratio of the output signal SG1 and shortens the activated time of the output transistor 3. This decreases the charging current I2 and the potential of the second voltage signal SG4 and increases the potential of the second error output signal SG5. Furthermore, this causes the duty control signal SG8 to remain high for a long period (i.e., having a high duty ratio). That is, an increase in the potential of the second error output signal SG5 shortens the period during which the potential of the triangular wave signal SG7 exceeds the potential of the error output signal SG3.
The increase in the duty ratio of the duty control signal SG8 decreases the duty ratio of the output signal SG1 and prolongs the activated time of the output transistor 3. This increases the charging current I2. Such operation is repeated until the charging current I2 sent to the battery BT converges on a predetermined value. That is, until the second voltage signal SG4 converges on the second reference voltage Vref2.
If the output voltage Vout2 of the battery BT increases, the potential of the third error output signal SG6 decreases. When the potential of the third error output signal SG6 becomes smaller than the potentials of the first and second error output signals SG3, SG5, the comparison circuit 16 compares the third error output signal SG6 with the triangular wave signal SG7 and generates a duty control signal SG8 that remains high for a short period (i.e., has a low duty ratio). In other words, an increase in the potential of the third error output signal SG6 prolongs the period during which the potential of the triangular wave signal SG3 exceeds the potential of the error output signal SG6.
The decrease in the duty ratio of the duty control signal SG8 increases the duty ratio of the output signal SG1 and shortens the activated time of the output transistor 3. This decreases the charging current I2 and the output voltage Vout2 and increases the potential of the third error output signal SG6. Furthermore, this causes the duty control signal SG8 to remain high for a long period (i.e., have a high duty ratio). That is, an increase in the potential of the third error output signal SG6 shortens the period during which the potential of the triangular wave signal SG7 exceeds the potential of the error output signal SG6.
The increase in the duty ratio of the duty control signal SG8 decreases the duty ratio of the output signal SG1 and prolongs the activated time of the output transistor 3. This increases the charging current I2 and the output voltage Vout2. Such operation is repeated until the output voltage Vout2 of the battery BT converges on a predetermined value. That is, until the output voltage Vout2 converges on the third reference voltage Vref2.
FIG. 2 is a graph showing the relationship between the current and voltage of the AC adapter 4. The AC adapter 4 maintains the DC power supply voltage Vin constant as the supply current I0 increases. When the supply current I0 reaches the overcurrent value I.sub.limL (point P1), the overcurrent limiter is activated. This causes the AC adapter 4 to decrease the DC power supply voltage Vin. When the supply current I0 reaches a maximum limit value I.sub.limH (point P2), the AC adapter 4 shifts to a shut-down state. As a result, the DC power supply voltage Vin continues to decrease and the supply current I0 starts to decrease.
The DC--DC converter 100, which uses the AC adapter 4, maintains the output voltage Vout2, which is lower than the DC power supply voltage Vin, constant as the charging current I2 increases. When the charging current I2 reaches a predetermined value (point P3), the DC--DC converter 100 maintains the charging current I2 constant while decreasing the output voltage Vout2.
The first to third reference values Vref1-Vref3 are set so that the current supply capacity of the AC adapter 4 can be fully utilized.
However, the employment of an AC adapter having a current supply capacity that differs from that of the AC adapter 4 may lead to the shortcomings described below.
(1) If an AC adapter having a current supply capacity smaller than that of the AC adapter 4 is employed, the AC adapter is apt to enter an overcurrent state since the supply current I0, which is set in accordance with the AC adapter 4, easily exceeds the current supply capacity of the AC adapter. That is, the AC adapter enters a shut-down state whenever the supply current I0 exceeds the maximum limit value I.sub.limH. Thus, the employment of such an AC adapter in electronic equipment using the DC--DC converter 100 is not preferable.
(2) If an AC adapter having a current supply capacity greater than that of the AC adapter 4 is employed, the current supply capacity of the AC adapter cannot be used fully even if the supply current I0 reaches the maximum value. Thus, the current supply capacity of the AC adapter cannot be put to full use.
Accordingly, a second prior art DC--DC converter 120, shown in FIG. 3, has been proposed. The DC--DC converter 120 has a switch SW which selects a first reference voltage Vref1 from a plurality of reference voltages in accordance with the current supply capacity of the AC adapter. By altering the reference voltage, the supply current I0 of the AC adapter can be optimally adjusted. In this case, the switch SW is shifted by a control signal from the AC adapter. Accordingly, the AC adapter is required to have a special device. This increases the cost of the AC adapter. The switch SW also increases the cost of the DC--DC adapter.